Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance

ABSTRACT

A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

BACKGROUND

1. Field of the Invention

The invention relates to simulation and testing of integrated circuitperformance, and more particularly to segment scan simulation ofintegrated circuit element performance.

2. Background Art

In the design of a large scale microprocessor, with many issues ofcomplex architectural design, circuit design, CAD design, and photomaskdesign, a successful functional scan verification of the many elementsof the microprocessor becomes critical to the successful reduction ofthese elements to a Release Instruction Tape (“RIT”). One way ofaccomplishing design and fabrication verification is through the use ofa scan ring. A scan ring, designed into the microprocessor, is a chainof serially connected latches. In this context, the chain or chains ofserially connected latches are used for initialization and/or debug ofthe microprocessor.

However, if the scan ring is defective or broken, basic access to thedevice is limited and quick accurate diagnosability becomes a severeproblem. Therefore, the scan ring's scannability is often simulated andverified before the design gets reduced to a Release Instruction Tape.The scan ring's scannability is deemed verified if the scan ring isshifted once completely around the scan ring and each latch on the ringretains its initial scan data at the end of shifting.

If the full scan ring fails to rotate (shift) successfully, there areseveral methods used traditionally to detect and diagnose the specificbroken area of the scan ring. However, these methods are not only timeconsuming, but they may fail to detect the broken ring duringsimulation.

Thus, a clear need exists for an improved apparatus and method fordiagnosing the broken functional rings of the microprocessor.

SUMMARY OF THE INVENTION

The simulation method, system, and program product of our inventionbuilds upon the underlying hardware design of the microprocessor. Themethod, system, and program product stops normal functions of asimulation testcase, starts the scan clocks, and records a first “snapshot” of the scan ring data at this initial time. The hardware logicthen rotates (shifts) the scan ring using the current scan data, andwhen the scan clock stops (where the stop of the scan clock iscontrolled based on the number of latches on the scan ring), another“snap shot” of scan ring data is taken. According to our invention, the“snap shots” are compared and if both of the “snap shots” are identicalthe functional scan is successful. But if the functional scanverification fails to rotate the scan chain correctly, that is, if someof the latches do not match in the two “snap shots,” it becomesnecessary to locate the broken spot within the large number of scanlatches. Several methods have heretofore been used to identify suchproblem latches.

One method is to rerun the testcase with the same scan scheme, andduring the rotation (shift) of the scan, adding an extra check tocompare the transition of every pair of latches. If an unexpectedtransition is seen, this unexpected transition can pinpoint a defectivelatch. But such methods are inherently time-consuming, comparing thewhole scan ring each time the scan clock advances by 1 clock. If thereare million latches on the scan ring, it will take 1 million latchesmultiplied by another 1 million checks to locate the defective latch.

Another method is to set initial pattern of 0101, such that every evenlatch stores a 0 and odd latch stores a 1, and clocking the scan ring byone A/B scan clock. The final value of the latch is checked and comparedwith the expected data. But this method also presents its own defect. Ifa circuit is designed incorrectly and has some other value thatoverrides the scan data, this patterning method can fail to detect thefailing spot.

A third method is to check that a single latch is moving along the scanring during the rotation (shifting). This method has the same problem asthe second method, described above.

To combine the advantages of each of the methods above, we describe aparallel sectional scan method, system, and program product. The scanring is subdivided into several sections. An initial value may beoptionally stored in the beginning of each scan section. As each scanclock advances, the transition of each latch is monitored. And, giventhe number of sections, these sections can be spun off to do checkingusing different threads. This method has the advantage of being able tomonitor latches during each step of the scan and is resistant to theperformance problems of the prior art by using different threads.

THE FIGURES

Various aspects of our invention are illustrated in the Figures appendedhereto.

FIG. 1 is an illustration of functional scan verification with aselected random simulation testcase, where the normal function clocksare stopped and individual scan clocks are started to start the shiftingof the scan data around the scan ring, with “snap shots” of the scandata for the latches being taken. This is followed by a subsequent setof “snap shots” of the scan data to compare with the initial snap shot.Thereafter, the scan clocks are stopped and the normal function clocksare restarted again for the normal simulation testcase to continue.

FIG. 2 illustrates the basic connections of the processor latches forfunctional scan verification of a processor. FIG. 3 illustrates twomethods of locating the broken chain if a functional scan fails. Onemethod compares all of the latches to their expected shifted values inevery scan. In the alternative method, when the normal function clocksare stopped, the initial pattern is stored into the scan chain so thateach even latch has a value of 0, each odd latch has a value of 1, andonly L2 latches of the scan chain are used in this case.

FIG. 4 shows another method of locating the broken chain if thefunctional scan fails. The illustrated method shows checking oneparticular set of scan latch data that is moving along the scan chain.As there shown, a particular latch is picked from the scan chain, andits value is monitored during the shifting of the ring. Then, asubsequent latch is checked against this expected value during the scan.The broken location can be located where unexpected scan data isdetected. This method can be used if a known area is suspected to bebroken.

FIG. 5 illustrates a parallel scan exemplification where the scan ringis divided into a number of sections where, during each A/B clock, eachsection can be spun off to another thread for comparing the transitionvalues between two latches.

FIG. 6 illustrates the generation of a scan chain that feeds into thefunctional scan verification. The illustrated method traces the logic tofind the connected scan latches in the logic which are fed from themodel inputs. If there is no broken logic, the scan chain is generatedsuccessfully as a scan ring.

FIG. 7 shows the three different exemplifications of the parallelsectional scan method.

DETAILED DESCRIPTION

The simulation method, system, and program product of our inventionutilizes the underlying hardware design of the microprocessor toself-test the microprocessor. Specifically, the method, system, andprogram product stops normal functions of a simulation testcase, andstarts the scan clocks, records a first “snap shot” of the scan ringdata at this initial time. The hardware logic then rotates (shifts) thescan ring using the current scan data, and when the scan clock stops(where the stop of the scan clock is controlled based on the number oflatches on the scan ring), takes another “snap shot” of scan ring data.

According to our invention, these “snap shots” are compared and if bothof the “snap shots” are identical the functional scan is deemedsuccessful. But if the functional scan verification fails to rotate thescan chain correctly, that is, if some of the latches do not match inthe two “snap shots,” it becomes necessary to locate the broken spotwithin the large number of scan latches.

FIG. 1 shows the general purpose of the functional scan verification. Asshown in FIG. 1, random simulation testcase 100 is selected. Thetestcase could start with the normal simulation function. As part of theprocedure, the normal function clocks are stopped and scan clocks arestarted 101 to start the shifting of the scan data around the scan ring.At this time, the snap shots of the scan data for the total latches aretaken. When the scan ring has been completely shifted, another snap shotof the scan data for the latches is taken 102. This subsequent snap shotis compared to the initial snap shot. At this time, the scan clocks arestopped and the normal function clocks are restarted again for thenormal simulation testcase to continue. If the functional scan issuccessful, the testcase will be ended successfully given that it was afunctionally successful scantest.

FIG. 2 shows a high level representation of the basic connections of theprocessor latches. Element 200 contains all of the latches in theprocessor, where latch 201 is the first latch in the scan ring or chainand connects to a universal input pin. Latch 202 is the last latch inthe scan ring that connects to an universal scan output pin which alsoconnects to a universal scan in pin. Each latch consists of L1/L2latches. All of the latches are gated by normal function clocks and scanclocks. The L1/L2 latch is typically gated by scan A/B clocks. When scanA clock is on, scan data is shifted into L1 latch. And when B clock ison, the scan data is shifted into the L2 latch. Normally, a separateprogram is run to generate a latch file containing all the connectedlatch facilities from the first latch to the last latch of theprocessor.

FIG. 3 shows two methods of locating the broken chain if the functionalscan fails. Element 300 is a method that compares all the latches to itsexpected shifted values in every scan A/B clocks. The previous values ofeach L2 latch are saved. When scan B clock is on, the current latchvalue is obtained and compared to its precedent latch's previous valuetogether with its polarity. If there is miscompare, the latch isdefective. Elements 301 and 302 show that only the L2 latches need to beconsidered in this case. Element 303 is a checking step during scanbetween two L2 latches. This method finds the defective latch during thefunctional scan. But if the processor is a very large design and thismethod can be very time consuming since during the shift of each scanclock, every transition of the latch on the scan ring is checked.

Element 304 represents another method used to detect the broken scanchain. When the normal function clocks are stopped, the initial patternof 0101 is stored into the scan chain so that each even latch has valueof 0, and each odd latch has value of 1. Only L2 latches of the scanchain are used in this case. The scan chain is shifted by one of the A/Bclocks. At the end of one A/B clock, all the latches are expected tohave opposite scan data. This method can point out whether the L1/L2transition within a latch is broken.

FIG. 4 shows another method of locating the broken chain if thefunctional scan fails. Element 400 illustrates the method of checkingone particular scan latch data that is moving along the scan chain. Inthis method, before the scan starts, one particular latch is picked fromthe scan chain. Its value is monitored during the shifting of the ring.The subsequent latch is checked against this expected value during thescan. The broken location can be located if unexpected scan data isdetected. If the particular latch 401 is picked carefully, the length ofsimulation can be shortened to find the defective latch. This method canbe used if a known area is suspected to contain a broken latch.

FIG. 5 illustrates a parallel sectional scan method. In this method, thescan ring is divided into a number of sections chosen by the user.(There are three sections in this case, Section 501, Section 502 andSection 503). The scan A/B clocks clock the number of latches in thering. The first latch of each section is optionally stored with a 1initially. During each A/B clock, each section can be spun off toanother thread for comparing the transition values between two latches.Alternatively, only one of these three sections can be selected formonitoring. Or, these three sections of latches can be monitoredsimultaneously using three different threads.

FIG. 6 shows the generation of the scan chain that feeds into thefunctional scan verification 604. Element 603 is a scan generation(scangen) program that looks into a simulation model 601 that was builtfor the hardware. The program traces the logic to find the connectedscan latches in the logic which are fed from the model inputs. If thereis no broken logic, the scan chain is generated successfully as a scanring. This scan ring contains a list of hardware facility names storedin a file 602 which is later used to verify the rotation of the ring.

FIG. 7 shows the three different ways of using the parallel sectionalscan method. Element 701 represents the initial set up. The method takesa random testcase and a scan chain model input. It saves the initialvalues of the scan ring in a data structure that contains the currentvalue, the previous value, the inverting next, the starting bit, and thename of the latch before the scan clocks start. A configuration file isprovided for user to select number of sections of the ring, threads, orwhether a particular section of the ring needs to be monitored. Ifmultiple threads are selected 702, the scan ring is subdivided intomultiple sections and each section is sent off to be monitored indifferent threads 705. If only one section is selected 703, only thetransition of that section is monitored only. If only one section of thering is to be rotated, after rotating the section, the comparison ofsnapshots in element 707 provides the resulting pattern of the rotationof the ring compared to the initial pattern of the ring.

The invention may be implemented, for example, by having the segmentscan simulation engine as a software application (as an operating systemelement), a dedicated processor, or a dedicated processor with dedicatedcode. The segment scan simulation engine executes a sequence ofmachine-readable instructions, which can also be referred to as code.These instructions may reside in various types of signal-bearing media.In this respect, one aspect of the present invention concerns a programproduct, comprising a signal-bearing medium or signal-bearing mediatangibly embodying a program of machine-readable instructions executableby a digital processing apparatus to perform a method for segment scansimulation.

This signal-bearing medium may comprise, for example, memory in aserver. The memory in the server may be nonvolatile storage, a datadisc, or even memory on a vendor server for downloading to a processorfor installation. Alternatively, the instructions may be embodied in asignal-bearing medium such as the optical data storage disc.Alternatively, the instructions may be stored on any of a variety ofmachine-readable data storage mediums or media, which may include, forexample, a “hard drive”, a RAID array, a RAMAC, a magnetic data storagediskette (such as a floppy disk), magnetic tape, digital optical tape,RAM, ROM, EPROM, EEPROM, flash memory, magneto-optical storage, paperpunch cards, or any other suitable signal-bearing media includingtransmission media such as digital and/or analog communications links,which may be electrical, optical, and/or wireless. As an example, themachine-readable instructions may comprise software object code,compiled from a language such as “C++”.

Additionally, the program code may, for example, be compressed,encrypted, or both, and may include executable files, script files andwizards for installation, as in Zip files and cab files. As used hereinthe term machine-readable instructions or code residing in or onsignal-bearing media include all of the above means of delivery.

While the foregoing disclosure shows a number of illustrativeembodiments of the invention, it will be apparent to those skilled inthe art that various changes and modifications can be made hereinwithout departing from the scope of the invention as defined by theappended claims. Furthermore, although elements of the invention may bedescribed or claimed in the singular, the plural is contemplated unlesslimitation to the singular is explicitly stated.

1. A method of simulating integrated circuit performance of a scan ringhaving a plurality of serially connected latches, comprising: 1)starting system scan clocks; 2) recording a first “snap shot” of scanring data; 3) starting a scan ring; 4) shifting the scan ring using thecurrent scan data; 5) stopping the scan clock and taking a second “snapshot”; and 6) comparing the “snap shots.”
 2. The method of claim 1wherein if both of the “snap shots” are identical the functional scan issuccessful.
 3. The method of claim 1 wherein if the “snap shots” are notidentical and thereafter locating a broken spot within the of scanlatches of the scan ring.
 4. The method of claim 3 wherein each latchcomprises L1L2 latches, gated by normal function clocks and scan clocks,wherein when scan A clock is on, shifting scan data into an L1 latch,and when scan B clock is on, shifting scan data into an L2 latch.
 5. Themethod of claim 3 comprising running a program to generate a latch filecontaining all the connected latch facilities from the first latch tothe last latch of the processor.
 6. The method of claim 3 comprisinglocating a broken chain if the functional scan fails, comprising thesteps of 1) comparing the latches to their expected shifted values inevery scan AB clocks. 2) saving previous values of each L2 latch; and 3)obtaining a current latch value and comparing it to its precedentlatch's previous value.
 7. The method of claim 3 comprising stoppingnormal function clocks, storing the initial pattern of 0101 into thescan chain whereby even latches have a value of 0, and odd latches havea value of 1; shifting the scan chain is by one AB clock, whereby at theend of one AB clock, all the latches are have opposite scan data if thescan chain is unbroken.
 8. The method of claim 3 comprising selectingone latch from the scan chain, monitoring the value of the latch duringshifting of the ring, and checking a subsequent latch against thisexpected value during the scan.
 9. The method of claim 8 comprisingshortening the length of the simulation chain to isolate the defectivelatch.
 10. The method of claim 3 comprising dividing the scan ring intoa plurality of sections, clocking the number of latches in the scanring, monitoring the sections, and comparing transition values betweentwo latches.
 11. The method of claim 10 comprising monitoring thesection in separate threads.
 12. A program product containing computerreadable program code on a substrate, said computer readable programcode controlling an integrated circuit for simulating integrated circuitperformance of a scan ring having a plurality of serially connectedlatches, by a method comprising: 1) starting system scan clocks; 2)recording a first “snap shot” of scan ring data; 3) starting a scanring; 4) shifting the scan ring using the current scan data; 5) stoppingthe scan clock and taking a second “snap shot”; and 6) comparing the“snap shots.”
 13. The program product of claim 12 wherein if both of the“snap shots” are identical the functional scan is reported to besuccessful.
 14. The program product of claim 12 wherein if the “snapshots” are not identical and thereafter locating a broken spot withinthe of scan latches of the scan ring.
 15. The program product of claim14 wherein each latch comprises L1L2 latches, and said computer readableprogram code gates each latch normal function clocks and scan clocks,wherein when scan A clock is on, shifting scan data into an L1 latch,and when scan B clock is on, shifting scan data into an L2 latch. 16.The program product of claim 14 wherein said program code runs a programto generate a latch file containing all the connected latch facilitiesfrom the first latch to the last latch of the processor.
 17. A programproduct containing computer readable program code on a substrate, saidcomputer readable program code controlling an integrated circuit forsimulating integrated circuit performance of a scan ring having aplurality of serially connected latches by a method comprising whereinsaid program code contains code for: a) starting system scan clocks; b)recording a first “snap shot” of scan ring data; c) starting a scanring; d) shifting the scan ring using the current scan data; e) stoppingthe scan clock and taking a second “snap shot”; and f) comparing the“snap shots;” g) if both of the “snap shots” are identical thefunctional scan is successful, but if the “snap shots” are notidentical, locating a broken chain if the functional scan fails, by amethod comprising the steps of 1) comparing the latches to theirexpected shifted values in every scan AB clocks; 2) saving previousvalues of each L2 latch; and 3) obtaining a current latch value andcomparing it to its precedent latch's previous value.
 18. The programproduct of claim 17 wherein said program code contains code for stoppingnormal function clocks, storing the initial pattern of 0101 into thescan chain whereby even latches have a value of 0, and odd latches havea value of 1; shifting the scan chain is by one AB clock, whereby at theend of one AB clock, all the latches are have opposite scan data if thescan chain is unbroken.
 19. The program product of claim 17 wherein saidprogram code contains code for selecting one latch from the scan chain,monitoring the value of the latch during shifting of the ring, andchecking a subsequent latch against this expected shifted value duringthe scan.
 20. The program product of claim 19 comprising program codefor shortening the length of the simulation chain to isolate thedefective latch.
 21. The program product of claim 17 comprising programcode for dividing the scan ring into a plurality of sections, clockingthe number of latches in the scan ring, monitoring the sections, andcomparing transition values between two latches.
 22. The program productof claim 21 comprising program code for monitoring the section inseparate threads.
 23. An integrated circuit having a scan ring thereinhaving a plurality of serially connected latches, and adapted forsimulating integrated circuit performance by a method comprising: 1)starting system scan clocks; 2) recording a first “snap shot” of scanring data; 3) starting a scan ring; 4) shifting the scan ring using thecurrent scan data; 5) stopping the scan clock and taking a second “snapshot”; and 6) comparing the “snap shots.”
 24. The integrated circuit ofclaim 23 wherein if both of the “snap shots” are identical thefunctional scan is successful.
 25. The integrated circuit of claim 23wherein if the “snap shots” are not identical and thereafter locating abroken spot within the of scan latches of the scan ring.
 26. Theintegrated circuit of claim 25 wherein each latch comprises L1L2latches, gated by normal function clocks and scan clocks, wherein whenscan A clock is on, shifting scan data into an L1 latch, and when scan Bclock is on, shifting scan data into an L2 latch.
 27. The integratedcircuit of claim 25 adapted for running a program to generate a latchfile containing all the connected latch facilities from the first latchto the last latch of the processor.
 28. An integrated circuit having ascan ring therein having a plurality of serially connected latches, andadapted for locating a broken chain if the functional scan fails bysimulating integrated circuit performance by a method comprising thesteps of: a) starting system scan clocks; b) recording a first “snapshot” of scan ring data; c) starting a scan ring; d) shifting the scanring using the current scan data; e) stopping the scan clock and takinga second “snap shot”; and f) comparing the “snap shots;” g) if both ofthe “snap shots” are identical the functional scan is successful, but ifthe “snap shots” are not identical, locating a broken chain if thefunctional scan fails, by a method comprising the steps of 1) comparingthe latches to their expected shifted values in every scan AB clocks; 2)saving previous values of each L2 latch; and 3) obtaining a currentlatch value and comparing it to its precedent latch's previous value.29. The integrated circuit of claim 28 adapted for stopping normalfunction clocks, storing the initial pattern of 0101 into the scan chainwhereby even latches have a value of 0, and odd latches have a value of1; shifting the scan chain is by one AB clock, whereby at the end of oneAB clock, all the latches are have opposite scan data if the scan chainis unbroken.
 30. The integrated circuit of claim 28 adapted forselecting one latch from the scan chain, monitoring the value of thelatch during shifting of the ring, and checking a subsequent latchagainst this expected value during the scan.
 31. The integrated circuitof claim 30 adapted for shortening the length of the simulation chain toisolate the defective latch.
 32. The integrated circuit of claim 28adapted for dividing the scan ring into a plurality of sections,clocking the number of latches in the scan ring, monitoring thesections, and comparing transition values between two latches.
 33. Theintegrated circuit of claim 32 adapted for monitoring the section inseparate threads.
 34. The program product of claim 17 wherein each latchcomprises L1L2 latches, and said computer readable program code gateseach latch normal function clocks and scan clocks, wherein when scan Aclock is on, shifting scan data into an L1 latch, and when scan B clockis on, shifting scan data into an L2 latch.
 35. The program product ofclaim 17 wherein said program code runs a program to generate a latchfile containing all the connected latch facilities from the first latchto the last latch of the processor.
 36. The integrated circuit of claim28 wherein each latch comprises L1L2 latches, gated by normal functionclocks and scan clocks, wherein when scan A clock is on, shifting scandata into an L1 latch, and when scan B clock is on, shifting scan datainto an L2 latch.
 37. The integrated circuit of claim 28 adapted forrunning a program to generate a latch file containing all the connectedlatch facilities from the first latch to the last latch of theprocessor.